1. Field of the Invention
The invention relates generally to the field of integrated circuit interconnection devices and methods.
More specifically, the invention relates to an interface board, high density reroute layer or “cap chip” for applications requiring a larger number of electrical interconnects spaced closely together such as used in an interconnected stack of integrated circuit chips in the form of a multilayer electronic module.
2. Description of the Related Art
By way of background, the U.S. Patents cited below disclose inventions wherein layers containing integrated circuits chips are stacked and electrically coupled or interconnected using any of a number of stacking techniques known to those skilled in the art. For example, Irvine Sensors Corporation, now ISC8 Inc., assignee of the instant application, has developed several patented techniques and devices for stacking and interconnecting multiple integrated circuits. Some of these techniques and devices are disclosed in U.S. Pat. Nos. 4,525,921; 4,551,629; 4,646,128; 4,706,166; 5,104,820; 5,347,428; 5,432,729; 5,688,721; 5,953,588; 6,117,704; 6,560,109; 6,706,971; 6,717,061; 6,734,370; 6,806,559 and 8,074,082.
This invention relates to the fabrication of three-dimensional electronic packages in which a multiplicity of individual integrated circuit (IC) chips are secured together in a stack which provides a very high density electronic package.
As stated in U.S. Pat. No. 5,279,991, which provides more detailed disclosure of certain process steps, the assignee of this application pioneered the use of IC chip stacks; first as modules providing photo-detector focal plane circuitry and then as units suitable for computer memories and the like. U.S. Pat. Nos. 4,525,921 and 4,646,128 relate to the stacks designed for general use as memory devices and other non-focal-plane packages.
One problem, which applies to stacks used as memory devices and also to other non-focal-plane packages, is the difficulty of connecting exterior circuitry to the large number of conductors on the lateral surfaces, i.e., access planes of the completed stack. Focal plane chip stack modules incorporate multiplexer circuitry, which greatly reduces the number of module output connections. However, providing output connections for memory devices and other non-multiplexed devices is a much greater challenge.
There are two acknowledged orientations which represent the structural relationship of the stacked IC chips in a module to the lead-out or I/O layer, which makes outside electrical circuitry available for connection to the multiplicity of electrical leads (terminals) which are formed on the access plane face of the module, and which are electrically coupled to the IC circuitry embedded in the module.
In one arrangement, the layers of the module extend in planes perpendicular to the plane of the I/O layer. And in the other arrangement, the layers of the module extend in planes parallel to the plane of the I/O layer.
The I/O layer may be located below, above, or along the side of, the stacked chip module. The two most common configurations are described as a “sliced bread” stack, or as a “pancake” stack.
U.S. Pat. No. 4,706,166 discloses a “sliced bread” stack in which the IC chips in the stacked module are in planes perpendicular to a stack-supporting I/O layer. The I/O layer carries electrical conductors, which are used to connect the module to external circuitry such as a printed circuit board. The access plane of the stack faces the supporting I/O layer. The electrical connections between the stack face and I/O layer are formed by bonding aligned solder bumps on the opposing surfaces, a process is sometimes referred to as surface mount technology. In such a construction, the lead-out terminals are necessarily located very close to one another, a fact which creates difficulties in obtaining satisfactory lead-out connections.
“Pancake” stacks comprise IC chips which are in planes parallel to a supporting I/O layer. The electrical leads from the many terminals on the access plane of the stack preferably are brought either to the bottom or to the top of the stack, in order to be connected to external circuitry. An example of such a “pancake” stack is disclosed in U.S. Pat. No. 5,279,991. “Pancake” stacks, as distinguished from “sliced bread” stacks, are more likely to be used where a smaller number of IC chips are included in the stacked layer module; either because fewer chips are needed for a particular module or because of limited “headroom” i.e., limited available space in which the module is located.
The present invention deals primarily with the problem of connecting the circuitry of IC chips in pancake stacks with suitable lead-out terminals, which are then used in connecting to external circuitry.
Generally speaking, substantially planar layer elements containing integrated circuits are bonded together one on top of another so as to provide a footprint equivalent to that of the largest layer in the stack. Selected input/output connections of the integrated circuit die in the layers may be routed to the edges of the layers or to area interconnects or electrically conductive vias defined in one or more of the layers using metalized traces using a set of known photolithographic steps.
“T-connect” structures for interconnecting one or more layers may be defined on one or more lateral surfaces of the stacked module by electrically routing and electrically coupling the input/output connections of the ICs in the layers to the edges whereby the input/output connections are electrically accessible on the sides of the component stack in the form of a cross-sectional portion of the trace. These input/output connections are then electrically interconnected on one or more lateral surfaces of the component stack using photolithographic and conductive plating processes to create T-connects using techniques such as those described in the patents identified above.
Alternatively, electrically conductive vias may be defined at predetermined locations on one or more layers and used to electrically interconnect layers in the stack.
Advanced chip/die stacking/laminating technology often requires the use of interface boards also known as “cap chips”, having internal and external electrical connections with a requirement of large numbers of closely spaced interconnections sometimes referred to as “fan-out connections. This requirement is not easily met using present printed circuit board (PCB) technology, or by other methods due to the small dimensions involved.
As earlier discussed, the die stacks use metalized conductive traces running on the side walls of the stack (“side bus”) which connect to individual layer traces in the form of access leads disposed on the surface of each die. These layer traces terminate at the perimeter or edge of the layer where the cross-section of the traces is exposed prior to application of the side buses.
To connect die stacks to other devices or assemblies, side buses may be provided to terminate at an interface board or cap chip or reroute layer within which high density re-routing of contacts is achieved in order to connect to external circuitry.
It is the interface board/cap chip that this invention addresses. The invention is comprised of multiple, stacked metal bumps (called “stud bumps”) from an automatic wire bonder used to create solid via contacts and uses lithography to re-route the traces within the device.
The cap chip and reroute layer of the invention may be provided to be of identical footprint dimensions as the stacked/laminated die and either of the same thickness or slightly thicker, depending on its application.